1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more specifically to dual port memory devices.
2. Description of the Prior Art
Computer systems utilize cache memories to enhance system performance. A data cache contains the cached data, and a cache tag memory contains the addresses of data stored in the cache. A processor, when making a memory access, accesses the desired memory location through the cache. If the desired location is already in the cache, access is complete. If it is not, the memory location is fetched from main system memory and loaded into the cache.
The speed of the integrated circuit devices used in the cache are important. The cache tag memory must provide a hit or a miss signal for every memory access by the processor. If the cache tag memory is slightly slow, the performance of the entire system suffers.
As is known in the art, one technique to improve the operating speed of integrated circuit devices is to reduce or balance stray capacitances. Memories have relatively long bit lines which contribute significantly to such capacitances. Good device design can help minimize such capacitances, but the nature of a memory device causes inevitable problems. Therefore, balancing of bit lines in a memory device layout is important.
No successful design has previously been done for a dual port cache tag memory device. In such a device, the capacitances for two sets of bit lines must be considered. In addition to stray capacitances, coupling capacitances between bit lines for the two ports can adversely impact device performance. In a dual port cache tag memory, in which speed is important, the extra problems caused by the extra bit lines can be significant.
Any device used in specialty designs such as cache tag memories must take special device functions into consideration. For example, cache tag memories must occasionally be cleared. One technique for clearing cache memories utilizes a flash clear, which clears only a single bit position within the memory. The cleared bit position is reset for all entries in the memory simultaneously. This allows the entire memory to be reset in a single step.
Special functions such as flash clear must be properly handled by any device design. Designs which improve device speed often do so at the expense of being able to handle more complex functions. Devices which can perform more complex functions such as flash clear often must sacrifice speed in order to do so.
It is known that memory devices can have non-functional bits as a result of processing variations. Rather than simply discard devices which have a small number of bad bits, redundant memory cells are usually provided on the device. These may be provided in the form of redundant rows or columns. The columns containing bad bits are disabled, typically by blowing fuse links, and the redundant columns are enabled to take their place. Mapping must be done in order to allow the redundant memory to substitute for bad regions anywhere on the device.
It would be desirable to provide a redundant memory scheme suitable for use with a dual port memory device. Such a scheme should be compatible with the use of the device as a cache tag memory. Preferably, the redundant memory is implemented in a manner compatible with enhancing device performance by minimizing stray and cross coupling capacitances. The redundant memory should be capable of being mapped to any location on the device which contains non-functional memory cells, and incorporating it into the device should not add significant complexity to the overall device design.